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Strings in Verilog

A quick reference on a couple of ways to manipulate strings in Verilog HDL.

Declaration

There is no string data type is Verilog, so use the following to declare a register to hold a string.

reg[n*8:0] string;

Where the maximum length of the string is n characters. It takes 8 bits to store each character.

Usage

string = "Hello World"; $sdisplay("%s", string); // will get "Hello World"

Also, normal concatination will work, for the most part. So something like:

string = {"/path/to/file","/","filename",".txt"};

will result in a string useful to pass to $open to open a file.

For anything more advanced, a very good function is

$sformat(string,"%s %d %s",str1,num,str2);

would produce the string with the three varibles concatinated together and spaces in between.


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