Dual Parallel FFT

Key Features

Key features of the dual parallel FFT IP Core

• Fastest most power efficient architecture optimized for 128 to 4096 points FFTs
• Optimized Butterflies/Dragonflies, reductions from constant twiddle factors reduces logic
• No pipeline limit, fully asynchronous to maximum pipeline stages
• upto 32 points in/out per clock cycle, ultra high performance, 12.5 GSPS+ possible in FPGA
• lengths up to 4096 points practical in FPGAs

Performance

Performance example for the Parallel FFT IP Core with the following features:

• Virtex-5
• 400 MHz clock
• 32 bit complex I/O (16 real/imag)
• Speed is in GSPS (giga samples per second)

Block Diagram

Block diagram of an example of the Dual Parallel FFT IP Core.

Device Fit Estimate or Additional Information

Fill out the FFT IP Fit/Information Form to obtain a device usage estimate in your target technology or to obtain additional information about a specific FFT architecture.