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Mixed Radix FFT
Efficient FPGA or ASIC implementations for any FFT length and frequency bin width.
Radix-2 or -4 FFT algorithms lend themselves nicely to parallel FPGA or ASIC logic implementation. However, real-world processing often requires non power-of-2 or -4 FFT lengths for spacing into the desired frequency bin size, called mixed-radix FFTs.
At Dillon Engineering, we have helped our customers achieve optimal mixed-radix FFT solutions, with design considerations such as:
- Combination parallel and serial FFT engines
- Continuous data processing
- Latency constraints
- Internal or external memory budget
Key Features
Key features of the mixed radix FFTÂ IP Core.- lengths other than radix-2 possible (i.e. 768, 256 x 3)
- Parallel FFT structures to increase performance
- Fixed or floating point math
- wide range of performance options
- Mixed radix-2, 3, 5, and 7 lengths available
Block Diagram
Block diagram of a Parallel Mixed Radix-2/3 FFT. An example of one of the many Mixed Radix FFT architectures Dillon Engineering has available.
Additional Information
For more information, see our HPEC 2003 Presentation on mixed-radix FFT processing.
DE Releases FFT_PIPE IP Cores for Xilinx FPGAs