FPLIC ParaCore Parameters
ParaCore Architect parameters for the Floating Point Library IP Core.
Dillon Engineering’s Floating Point Library IP Core contains all the elements required to implement a high-performance floating point system.
| MODULE |
PARAMETER |
TYPE |
DESCRIPTION |
Addition
Subtraction
Division
Multiplication
Reciprocal
Square Root |
type |
nType |
The nType definition is used to specify the width of the exponent and mantissa (see also the notes below) |
| special |
Boolean |
Set to True in order to implement IEEE 754 special-case tracking |
| stages |
Integer |
Specifies the number of pipeline stages to be used |
| Convert |
iType |
nType |
Specifies the input data type (see also the notes below) |
| oType |
nType |
Specifies the type of the output data (see also the notes below) |
| stages |
Integer |
Specifies the number of pipeline stages to be used |
|
The following table defines the nType parameter, which is used to define the number types to be implemented by ParaCore Architect:
| PARAMETER |
TYPE |
DESCRIPTION |
| type |
Select |
Select number type (options are int or float). |
| width |
Integer |
For type == int, this parameter sets the integer width. For type == float, this parameter is automatically set to e_width + m_width + 1 (see below). |
| e_width |
Integer |
When type == float, this parameter defines the width of the exponent (it should be set to 8 for single precision and 11 for double precision). |
| m_width |
Integer |
When type == float, this parameter defines the width of the mantissa (it should be set to 23 for single precision and 52 for double precision). |
|
Forgot your password?
New user?
FPLIC Specification
FPLIC Narrower Precision Archive
Dillon Ingenuity
FPLIC Riviera Evaluation
DE Releases FFT_PIPE IP Cores for Xilinx FPGAs