UltraLong FFT

As FFT lengths increase, FPGA and ASIC memory usage becomes more pervasive than logic usage. When the memory usage exceeds the on-chip memory capacity, it may require splitting the FFT algorithm processing and storing intermediate results in external memory. Here an "UltraLong FFT" is thus defined as an FFT length that exceeds the internal memory budget of the target device, necessitating data movement to external memory.

Block Diagram

Block diagram with external memory used for storage during the three required data transposes.

Versatile IP

At Dillon Engineering, we have provided our customers with efficient UltraLong FFT solutions, taking into consideration a number of design trade-offs, including:

• FFT engines with variable lengths and robust scaling options
• Continuous processing
• Resource sharing
• Overlapping data sets
• External SRAM or DRAM with on-chip caching where required
• Rotation stage via CORDIC or custom trigonometry methods

Performance

The performance of a 2D FFT is limited by the bandwidth of the external memory. Each UltraLong FFT IP Core delivered by Dillon Engineering is configured to obtain maximum performance based upon the external memory architecture available. Fast synchronous SRAM is best, as the transpose is slowed by DRAM.

More Information

See a recent UltraLong FFT IP Success and other news stories.

For details on UltraLong FFT algorithm processing, see our HPEC 2004 Presentation on the subject.

Device Fit Estimate or Additional Information

Fill out the FFT IP Fit/Information Form to obtain a device usage estimate in your target technology or to obtain additional information about a specific FFT architecture.