DE Releases Mixed Radix FFT IP Cores for Xilinx FPGAs
Product Announcement
Dillon Engineering announces the availability for immediate delivery of the Mixed Radix FFT IP Core for Xilinx FPGAs. This innovative IP core provides optimal performance for any FFT size through intelligent radix selection and combination.
Revolutionary Mixed Radix Architecture
The new Mixed Radix FFT IP Core represents a significant advancement in FFT technology. Unlike traditional radix-2 or radix-4 implementations that are optimized for specific FFT sizes, the Mixed Radix architecture automatically selects the optimal combination of radix types to maximize performance for any given FFT length.
Key Features
- Flexible FFT Sizes: Support for any power-of-2 FFT size from 64 to 65,536 points
- Automatic Radix Optimization: Intelligent selection of radix-2, radix-4, and radix-8 stages
- Minimal Resource Usage: Optimized for efficient FPGA resource utilization
- High Throughput: Maximum performance across all supported FFT sizes
- Low Latency: Reduced pipeline depth through optimal radix selection
- Configurable Precision: Support for both fixed-point and floating-point arithmetic
Technical Advantages
Optimal Radix Selection
The Mixed Radix architecture automatically determines the best combination of radix stages for each FFT size:
- Radix-2 stages: Used for maximum flexibility and minimal complexity
- Radix-4 stages: Employed to reduce butterfly stages and improve throughput
- Radix-8 stages: Utilized for maximum efficiency in specific configurations
Performance Benefits
| FFT Size | Radix Combination | Stages | Performance Improvement |
|---|---|---|---|
| 256 | Radix-4 x 4 | 4 | 2x vs Radix-2 |
| 512 | Radix-8, Radix-4, Radix-2 | 3 | 3x vs Radix-2 |
| 1024 | Radix-4 x 5 | 5 | 2x vs Radix-2 |
| 4096 | Radix-8 x 4 | 4 | 3x vs Radix-2 |
Target Applications
The Mixed Radix FFT IP Core is ideal for applications requiring flexibility and optimal performance:
- Software Defined Radio: Variable FFT sizes for different channel bandwidths
- Communications Systems: LTE, 5G, and Wi-Fi with multiple FFT configurations
- Spectrum Analysis: Flexible resolution bandwidth selection
- Radar Signal Processing: Adaptive FFT sizing for different modes
- Audio Processing: Various block sizes for different sample rates
- Test Equipment: Configurable FFT for versatile measurement capabilities
FPGA Resource Efficiency
The Mixed Radix architecture is optimized for minimal FPGA resource consumption:
Resource Comparison
Compared to traditional FFT implementations:
- LUT Reduction: 15-30% fewer LUTs than equivalent radix-2 designs
- DSP Optimization: Efficient use of DSP48 blocks
- Memory Efficiency: Reduced BRAM requirements through smart buffering
- Power Reduction: Lower dynamic power consumption
Xilinx Platform Support
The Mixed Radix FFT IP Core is fully optimized for all modern Xilinx FPGA families:
- Xilinx 7-Series (Artix-7, Kintex-7, Virtex-7)
- Xilinx UltraScale Architecture
- Xilinx UltraScale+ Architecture
- Xilinx Versal ACAP
Integration and Deliverables
The Mixed Radix FFT IP Core package includes:
- Synthesizable RTL source code (Verilog or VHDL)
- AXI4-Stream interface for easy integration
- Comprehensive testbench and verification environment
- Example designs for popular Xilinx development boards
- Complete technical documentation and user guide
- Performance characterization for all FPGA families
- Vivado IP Integrator support
Availability and Pricing
The Mixed Radix FFT IP Core is available for immediate delivery. Licensing options include:
- Single project license
- Multi-project license
- Site license for unlimited projects
- Source code availability
Evaluation and Purchase
An evaluation package is available for download, including encrypted IP with full functionality for simulation. Contact Dillon Engineering for pricing information, technical specifications, or to request an evaluation license.
Email: info@dilloneng.com
About Mixed Radix FFT Technology
Mixed Radix FFT algorithms have been used in software implementations for decades to achieve optimal performance. Dillon Engineering brings this flexibility to FPGA implementations with an intelligent, automated approach that selects the best radix combination for any FFT size without requiring manual optimization.
This technology represents years of development and optimization, leveraging Dillon Engineering's extensive experience in high-performance DSP implementations for FPGAs and ASICs.
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