Floating Point Library IP Core (FPLIC)
Overview
The Floating Point Library IP Core (FPLIC) from Dillon Engineering provides a comprehensive set of IEEE 754 compliant floating-point arithmetic operations optimized for FPGA implementation. These modules enable high-precision numerical processing in hardware with performance far exceeding software implementations.
Available Operations
➕ Addition/Subtraction
Single and double precision floating point add/subtract with full IEEE 754 compliance including denormalized numbers and exception handling.
✖️ Multiplication
High-performance floating point multiplier with optimized DSP48 block utilization and configurable latency.
➗ Division
Efficient floating point division implementation with configurable precision and throughput trade-offs.
√ Square Root
Hardware square root extraction with iterative or pipelined architecture options.
🔄 Conversion
Fixed-to-float, float-to-fixed, and format conversion operations (single ↔ double precision).
🔍 Comparison
Full suite of comparison operations (equal, less than, greater than) with proper NaN and infinity handling.
Technical Specifications
| Parameter | Single Precision | Double Precision |
|---|---|---|
| Format | 32-bit IEEE 754 | 64-bit IEEE 754 |
| Mantissa Bits | 23 bits | 52 bits |
| Exponent Bits | 8 bits | 11 bits |
| Dynamic Range | ~10^±38 | ~10^±308 |
| Precision | ~7 decimal digits | ~15 decimal digits |
| Add/Sub Latency | 6-8 clocks | 8-10 clocks |
| Multiply Latency | 4-6 clocks | 6-8 clocks |
| Divide Latency | 24-32 clocks | 54-64 clocks |
Key Features
- Full IEEE 754 Compliance: Complete support for normalized, denormalized, infinity, and NaN values
- Exception Handling: Proper handling of overflow, underflow, and invalid operations
- Rounding Modes: Support for all IEEE 754 rounding modes
- Optimized Performance: Pipelined architecture for maximum throughput
- Resource Efficient: Optimized use of FPGA resources including DSP blocks
- Flexible Configuration: Trade-off options between latency, throughput, and resources
- Easy Integration: Standard interfaces compatible with popular design flows
Performance Characteristics
Throughput
All floating point operations support high-throughput pipelined operation:
- Addition/Subtraction: One operation per clock cycle
- Multiplication: One operation per clock cycle
- Division: Configurable from 1 operation per N cycles to fully pipelined
- Square Root: Configurable from 1 operation per N cycles to fully pipelined
Clock Frequency
Achievable clock frequencies on modern Xilinx FPGAs:
| Device Family | Single Precision | Double Precision |
|---|---|---|
| Xilinx 7-Series | 300-400 MHz | 250-350 MHz |
| UltraScale | 400-500 MHz | 350-450 MHz |
| UltraScale+ | 450-600 MHz | 400-500 MHz |
Resource Utilization
Typical FPGA resource usage for single precision operations:
| Operation | LUTs | FFs | DSP48 | BRAM |
|---|---|---|---|---|
| Add/Subtract | ~500 | ~600 | 0 | 0 |
| Multiply | ~300 | ~400 | 2-3 | 0 |
| Divide | ~2000 | ~2500 | 2-3 | 0 |
| Square Root | ~1800 | ~2200 | 2 | 0 |
Applications
Scientific Computing
High-precision numerical applications:
- Physics simulations
- Computational fluid dynamics
- Climate modeling
- Molecular dynamics
Signal Processing
Advanced DSP algorithms requiring floating-point precision:
- Adaptive filtering
- Matrix operations
- Statistical analysis
- Machine learning algorithms
Graphics and Visualization
Real-time rendering and processing:
- 3D graphics pipelines
- Image processing
- Computer vision
- Video effects
Financial Modeling
High-speed numerical calculations:
- Risk analysis
- Option pricing
- Portfolio optimization
- Monte Carlo simulations
Design Considerations
Fixed-Point vs Floating-Point
Use Floating-Point When:
- Dynamic range requirements are high
- Precision requirements vary across the computation
- Algorithm development time is critical
- Porting from software implementations
Use Fixed-Point When:
- Resource constraints are tight
- Maximum performance is required
- Power consumption is critical
- Dynamic range is limited and known
Evaluation Package
A free evaluation package is available including:
- Pre-compiled encrypted libraries for simulation
- Comprehensive testbenches
- Example designs and integration examples
- Performance characterization data
- Complete documentation
Supported Simulators
- Xilinx Vivado Simulator
- ModelSim/QuestaSim
- Aldec Riviera-PRO
- Cadence Xcelium
Licensing Options
Flexible licensing to meet your project needs:
- Single Project License: Use in one commercial project
- Multi-Project License: Use across multiple projects
- Site License: Unlimited use within your organization
- Source Code License: Full RTL source code availability
Support and Services
Dillon Engineering provides comprehensive support:
- Integration assistance
- Performance optimization consulting
- Custom operation development
- Algorithm porting services
- Training and workshops
Get Started Today
Download the free evaluation package or contact Dillon Engineering for licensing information, technical specifications, or to discuss your floating-point FPGA design requirements.
Email: info@dilloneng.com