AES IP Core Introdution
Dillon Engineering’s AES Encryption/Decryption IP Core has been developed using our state-of-the-art ParaCore Architect™ utility. The result is a highly parameterized core that can be quickly and easily tailored to meet the size, performance, and data processing needs of any application. By means of ParaCore Architect, our AES IP Core can also be quickly and easily re-targeted towards any FPGA or ASIC implementation technology.
- ParaCore Architect parametric-based core provides maximum adaptability and flexibility (see details on the AES Parameters)
- Completely proven in many real-world applications
- Data throughput up to 12.8 Gb/s
- Complies with Federal Information Processing Standard (FIPS) 197
- Supports ECB, CBC, CFB, OFB, and CTR modes (NIST special publication 800-38A)
- Cores available for encryption, decryption, or combined encryption/decryption
- Key can be changed dynamically with no throughput penalty
- Several configurations available to trade throughput for area
- Available in generic HDL or targeted EDIF formats
- Delivered as a completely self contained module with a full testbench
The Dillon Engineering (DE) AES Library IP Core performs data encryption and/or decryption as specified by the Federal Information Processing Standard (FIPS) 197, Advanced Encryption Standard (AES). The HDL for the core is designed so it can be targeted toward FPGAs or ASICs. The AES Library IP Core addresses a wide range of throughput requirements by providing various levels of parallelism which trade throughput for area.
Device Fit Estimate
Fill out the AES IP Fit Form to obtain a device usage estimate in your target technology.