How-To documents to help you through everyday situations designing DSP logic for FPGAs and ASICs
Power calculation using XPower
Steps for power calculation using XPower and tips to calculate the power usage in large designs.
Strings in Verilog
A quick reference on a couple of ways to manipulate strings in Verilog HDL.
Inferring Block RAM vs. Distributed RAM in XST and Precision
This is a description of how to infer Xilinx FPGA block RAM or distributed RAM through HDL coding style and synthesis attributes/pragmas. Verilog GENERATE is an easy way to choose between the types without digging into the hierarchy. Verilog is the HDL of choice, and the tools are Xilinx XST (ISE 8.1) and Mentor Graphics Precision 2005c.99.
Verilog RTL Coding Style Guidelines, Tips, and Template
Many companies create Verilog coding standards, usually developing these in specification ("thou shall") format. Some standards or guidelines are available on the web. What is lacking with a specification is a generic template of actual Verilog that can be used to start creating consistent RTL. This document contains simple code and some of the most common RTL design components, with a few tips to help start making good, reusable Verilog RTL code. Disclaimer: this code does not do anything that makes any sense, and some of the signals aren't used or terminated, etc.