Load Unload FFT
FFT IP Core with a minimal memory footprint best suited for ASIC applications.
Key features of the Load Unload FFT IP Core
- Load, process, and unload cycles allow for a single set of data
- Minimal memory configuration best for least ASIC area
- 1, 2, or 4 butterfly configurations
- Optional input buffer for continuous data applications
- Fixed or floating point math
- Run-time length and direction selections
Review the Load Unload FFT Datasheet.
Device Fit Estimate of Additional Information
Fill out the FFT IP Fit/Information Form to obtain a device usage estimate in your target technology or to obtain additional information about a specific FFT architecture.