Dillon Engineering announces fft_float, a floating-point windowed FFT IP core for UltraScale+ FPGAs

October 28, 2026

Dillon Engineering has released fft_float, a run-time configurable FFT IP core that computes in IEEE-754 single-precision floating point from input to output, with a fully programmable window and input overlap of up to 50%.

fft_float transforms frames from 64 to 32K points, and more on larger devices, with the length selectable on every frame. Any window shape can be loaded as floating-point coefficients through a dedicated port and changed between frames. Floating-point arithmetic throughout removes the scaling analysis and overflow management that fixed-point FFTs require.

The number of parallel butterflies is a build option. A 4-butterfly configuration closes timing at 277.8 MHz on an AMD Kintex UltraScale+ KU5P while using under 5% of the device’s logic and DSP resources. Larger configurations trade resources for throughput.

fft_float is delivered as RTL source with a bit-accurate Octave model, a self-checking testbench that verifies every processing stage, simulation and synthesis scripts, and a user guide. It shares its parallel-butterfly architecture with Dillon Engineering’s fixed-point fft_64k core.

fft_float is available immediately under a project license. Full specifications, the block diagram and device utilization are on the fft_float product page. For pricing, contact us.