FFT IP cores#
Dillon Engineering’s FFT cores are parameterized, so one design can be built for the transform length, precision and throughput your system needs. They target both FPGAs and ASICs, and each is delivered with a bit-accurate C/C++ model and a testbench.
Compare the cores#
Core |
Architecture |
Data format |
Transform lengths |
Throughput |
|---|---|---|---|---|
Overlapped parallel butterfly, 32 radix-2 butterflies |
Fixed point, 12 to 32-bit I/Q (24 default); 16 to 24-bit twiddles |
Run-time selectable per frame, 64 to 65,536 points |
275 MSPS continuous in, 0 to 75% overlap |
|
Parallel butterfly, 4 to 16 radix-2 butterflies (build option); programmable window |
IEEE-754 single-precision floating point, end to end |
Run-time selectable per frame, 64 to 32K points (more on larger devices) |
Up to 222 MSPS in (4 butterflies), 0 to 50% overlap |
|
Pipelined radix-2, single butterfly per rank |
IEEE-754 floating point; fixed point of any width |
Run-time selectable, 32 to 64K points (legacy figure) |
Continuous streaming at Fmax |
|
Mixed radix, non-power-of-2 lengths |
— |
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|
Very long transforms using external memory |
Fixed or floating point |
— |
Scales with memory bandwidth |
|
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IEEE-754 single and double precision |
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Which core fits?#
- Long transforms with heavy overlap at a continuous sample rate
- Floating-point accuracy, a programmable window, and no scaling analysis
- Continuous streaming at the full clock rate
- Lengths that are not a power of 2
- Transforms too large for on-chip memory
- Wide dynamic range without fixed-point analysis
- Not sure, or something custom
Talk to us. Most cores can be modified quickly for a particular requirement.