fft_float: windowed floating-point FFT/IFFT#

New · AMD UltraScale+

Floating-point accuracy, FPGA throughput, any window you want. fft_float is a run-time configurable FFT/IFFT core that computes in IEEE-754 single precision from input to output, with a fully programmable window and up to 50% input overlap.

FP32 IEEE-754 single precision, end to end

277.8 MHz on Kintex UltraScale+, -1

Any window shape, loadable at run time

Overview#

fft_float is a run-time configurable FFT for AMD UltraScale+ FPGAs. The transform length can change on every frame, from 64 points up to the device’s memory limit; the reference build supports 32K points. The window is fully programmable: any shape can be loaded as N floating-point coefficients through its own port and clock, and reloaded between frames.

Because the arithmetic is floating point throughout, there is no scaling schedule to choose and no overflow to manage, and the dynamic range is that of single precision at every stage. The number of parallel butterflies is a build option, so the same design runs from a compact 4-butterfly core to a 16-butterfly high-throughput core.

Block diagram#

fft_float block diagram. One complex float sample per input clock enters an overlap buffer that also crosses into the processing clock domain, then a window stage with user-loaded float coefficients written on a separate coefficient clock, then an input buffer that bit-reverses and widens to 2B samples, then a parallel butterfly engine with B single-precision radix-2 butterflies, then an output buffer that returns natural-order data at one sample per processing clock.

Signal flow through fft_float, with its three clock domains.#

Overlap buffer

Accepts one sample per input clock, keeps the tail of the previous frame and builds each overlapped frame. It also moves the data into the processing clock domain.

Window

Multiplies each sample by its coefficient from a coefficient RAM loaded by the user.

Input buffer

Reorders the frame into bit-reversed order and widens it to 2B samples per clock for the engine.

Parallel butterfly engine

B single-precision radix-2 butterflies process each rank in place. It is the same engine architecture as the fixed-point fft_64k: overlapped 64K-point FFT/IFFT.

Output buffer

Returns the result in natural order, one sample per clock.

Features#

Floating point end to end

  • IEEE-754 single-precision complex data in, out and at every rank

  • Single-precision twiddle factors

  • AMD floating-point add and multiply operators, configurable pipelining

  • No scaling schedule and no overflow handling

Programmable window

  • Any window shape: N single-precision coefficients

  • Loaded through a simple write port (pointer reset plus write strobe)

  • Own clock domain; reload between frames

  • Applied to the overlapped frame, ahead of the transform

Flexible transform

  • Length selected per frame, 64 points up to the build maximum (32K in the reference build; larger maximums limited only by device memory)

  • Overlap per frame: 0, 1/8, 1/4 or 1/2; only new samples are supplied

  • FFT or IFFT selected per frame

Scalable throughput

  • Parallel radix-2 butterflies set at build time (built with 4 and 16)

  • Three independent clocks: input, processing/output, coefficient load

  • Processing clock can run faster than the input clock for higher overlap

  • Natural-order output, one complex sample per processing clock

Performance#

Reference build: 4 butterflies, 32K maximum length, Kintex UltraScale+ KU5P, -1 speed grade (the slowest). Processing clock 277.8 MHz, timing met.

The engine takes about \((N/2B)\log_2 N\) processing clocks per frame, and the output takes \(N\) clocks; a frame needs the larger of the two.

Transform length

Engine time (B = 4)

Frames/s, back to back

1,024

~1,280 clocks, 4.6 µs

~217,000

4,096

~6,144 clocks, 22 µs

~45,200

16,384

~28,672 clocks, 103 µs

~9,690

32,768

~61,440 clocks, 221 µs

~4,520

Maximum sustained input rate#

4 butterflies, 277.8 MHz processing clock:

Transform length

Overlap 0

Overlap 1/4

Overlap 1/2

1,024

222 MSPS

167 MSPS

111 MSPS

4,096

185 MSPS

139 MSPS

93 MSPS

16,384

159 MSPS

119 MSPS

79 MSPS

32,768

148 MSPS

111 MSPS

74 MSPS

These rates are calculated from the processing clock and the engine timing, not measured.

For example, with the input clock at 1/4 of the processing clock (69.4 MSPS of continuous input), the most demanding case, 32K points at 1/2 overlap, uses 61,440 of the 65,536 processing clocks available per frame. So even with only 4 butterflies, the full overlap range is supported at the longest length. More butterflies raise the engine rate proportionally: with 16, the engine is four times faster and the core is limited by its output, at about one sample per processing clock, for most lengths.

Device utilization#

4 butterflies, 32K maximum length, single precision. AMD Kintex UltraScale+ xcku5p-ffva676-1-e, Vivado 2025.2.1, post-route. Timing met at 277.8 MHz.

Resource

Used

Available

Utilization

CLB LUTs

9,478

216,960

4.4%

CLB registers

16,587

433,920

3.8%

Block RAM (36 Kb)

145

480

30.2%

UltraRAM

24

64

37.5%

DSP48E2

84

1,824

4.6%

Scaling with butterfly count#

Same device and settings, as an example of how resources grow with throughput:

Resource

4 butterflies

16 butterflies

Per added butterfly

LUTs

9,478

32,955

~1,960

Registers

16,587

54,173

~3,130

Block RAM (36 Kb)

145

276

~11

UltraRAM

24

64

~3.3

DSP48E2

84

324

20

The 16-butterfly, 32K build uses all 64 UltraRAMs of the KU5P; longer lengths or more butterflies at 32K need a larger device.

Fixed or floating?#

fft_64k: overlapped 64K-point FFT/IFFT (fixed point)

fft_float (floating point)

Arithmetic

24-bit fixed (12 to 32 bit)

IEEE-754 single precision

Length

64 to 64K

64 to 32K (device-limited)

Overlap

up to 3/4

up to 1/2

Window

none

programmable

Butterflies

32

4 to 16 (build option)

Input rate

275 MSPS, continuous

see the sustained-rate table

Clocks

1

3 independent

Scaling

per rank, per frame

not needed

KU5P use

44% LUT, 76% block RAM

4% LUT, 30% block RAM (4 butterflies)

Deliverables#

  • Synthesizable RTL source

  • Bit-accurate Octave model of the complete processing chain

  • Self-checking testbench that verifies the window output, the bit-reversed input, the FFT engine output and the final output against the model

  • Simulation and synthesis scripts

  • User guide

Applications#

  • Spectral analysis where wide dynamic range matters: radar, sonar, radio astronomy, test and measurement

  • Algorithms developed in floating point (GPU or CPU heritage) moved to an FPGA with no fixed-point conversion or scaling analysis

  • Windowed, overlapped spectrum estimation (Welch method) with application-specific windows

  • Frequency-domain processing where the window must change at run time

Availability and licensing#

fft_float is available immediately under a project license. Contact us with your transform lengths, overlap, window and target device for pricing.