fft_64k: overlapped 64K-point FFT/IFFT#

New · AMD UltraScale+

Long FFTs, full overlap, no dropped samples. fft_64k is a run-time configurable FFT/IFFT core that transforms 64 to 65,536 points at a continuous 275 MSPS, with up to 75% frame overlap.

Download the datasheet (PDF)

64K points, max length

275 MSPS continuous input

75% maximum frame overlap

Overview#

fft_64k is a high-throughput FFT/IFFT core for AMD UltraScale+ FPGAs. Length, direction, scaling and overlap can all change from frame to frame. Thirty-two radix-2 butterflies work in parallel, so the core keeps up with one complex sample per clock at 275 MHz, including frames that overlap by up to 75%.

The fixed-point datapath carries 12 to 32-bit I/Q (24 by default), with twiddle factors selectable from 16 to 24 bits. There is no processor bus and no registers to program: all settings travel with the frame, so there is no software in the loop and no reconfiguration time between frames. Results come out in natural order, four samples per clock. The core ships with a bit-accurate C and Octave/MATLAB model and a self-checking testbench, so you can predict the hardware output to the bit before you build anything.

Block diagram#

fft_64k block diagram. One sample per clock enters an overlap buffer, then an input buffer that bit-reverses and widens to 64 lanes, then a parallel butterfly engine with 32 radix-2 butterflies and 16 shared twiddle ROMs, then an output buffer that returns natural-order data at 4 samples per clock. A per-frame control and status path runs alongside.

Signal flow through fft_64k. Each frame’s settings travel with its data and come back with the output frame.#

Overlap buffer

Accepts one sample per clock and keeps the tail of the previous frame, combining it with the new samples to build each overlapped frame. Only the new samples need to be supplied. Held in UltraRAM.

Input buffer

Reorders each frame into bit-reversed order and widens it from 4 lanes to the engine’s 64 ports.

Parallel butterfly engine

Radix-2 decimation-in-time. 32 butterflies process one rank at a time, in place, from a 64-port processing buffer. Twiddles come from 16 dual-port octant ROMs, each shared by two butterflies. The sequencer adapts automatically to short lengths.

Output buffer

Returns the result in natural order, 4 samples per clock.

Features#

Flexible transform

  • 64 to 65,536 points (26 to 216), selected per frame

  • FFT or IFFT selected per frame

  • Overlap per frame: 0, 1/8, 1/4, 3/8, 1/2, 5/8 or 3/4

  • Per-rank scaling (divide by 2 at any stage), per frame

  • User tag returned with each output frame, along with its settings

Throughput

  • 1 complex sample per clock in, continuous: 275 MSPS at 275 MHz

  • Back-to-back frames with no gaps

  • 4 complex samples per clock out (1.1 GSPS), absorbing the data growth from overlap

  • 32 parallel radix-2 butterflies (64 data ports)

Precision

  • Fixed point, two’s complement

  • Data 12 to 32 bits per component (24 by default)

  • Twiddles of 16, 18, 20, 22 or 24 bits, chosen at build time

  • Rounding at each rank; RTL verified bit-exact against the model

  • Sticky arithmetic overflow detection

Efficient implementation

  • Octant-folded twiddle ROMs store 1/8 of the circle, bit-exact

  • Overlap buffer in UltraRAM, leaving block RAM for processing

  • Single clock, with clock crossings in place for a later split

  • Out-of-context core, ready to drop into a larger design

  • Maximum length set at build time (MAX_LOG2_N = 6 to 16)

Performance#

Kintex UltraScale+ KU5P, -1 speed grade (the slowest), 275 MHz.

Frame rate with continuous input:

Transform length

Overlap 0

Overlap 1/2

Overlap 3/4

1,024

268,555 /s

537,109 /s

1,074,219 /s

4,096

67,139 /s

134,277 /s

268,555 /s

16,384

16,785 /s

33,569 /s

67,139 /s

65,536

4,196 /s

8,392 /s

16,785 /s

Engine time for one transform is roughly \((N/64)\log_2 N\) clocks plus a small overhead: about 0.6 µs at 1K points and 60 µs at 64K. At 3/4 overlap the core produces four times as many transformed points as it takes in: a 275 MSPS input yields 1.1 G transformed points per second.

Maximum overlap by length#

Length

Maximum overlap

64

1/4

128

1/2

256

5/8

512 to 65,536

3/4

Short lengths are limited by per-rank pipeline latency, not by the arithmetic.

Numerical accuracy#

Estimated signal-to-quantization-noise ratio at the default widths (24-bit data, 18-bit twiddles) ranges from about 78 to 106 dB, depending on length, signal and scaling. The datasheet has latency, overlap limits and full numerical results.

Device utilization#

Full 64K-point build, 24-bit data, 18-bit twiddles, overlap enabled. AMD Kintex UltraScale+ xcku5p-ffva676-1-e, Vivado 2025.2, out-of-context, post-route. Timing met at 277.8 MHz.

Resource

Used

Available

Utilization

CLB LUTs

96,263

216,960

44.4%

CLB registers

61,697

433,920

14.2%

Block RAM (36 Kb)

363

480

75.6%

UltraRAM

16

64

25.0%

DSP48E2

96

1,824

5.3%

Results are from a single out-of-context run; in a full system they vary with placement and surrounding logic. A smaller maximum length or narrower data reduces memory use.

Deliverables#

  • Synthesizable RTL source and implementation constraints

  • Bit-accurate fixed-point model: pure Octave/MATLAB, and compiled C with an Octave/MATLAB (MEX) interface for speed

  • Self-checking SystemVerilog testbench, test-vector generator and test vectors; the regression covers every length, swept up and down, at every supported overlap

  • Simulation (Vivado xsim), synthesis and implementation scripts, with reference build reports

  • Status outputs for buffer overflow, missed frames and side-FIFO errors

  • User guide and full design document

Applications#

Radar

Pulse compression, range and Doppler processing on long, overlapped frames.

Lidar

Range and velocity processing where long transforms and continuous input matter.

Communications

OFDM, channelization and frequency-domain equalization across a wide range of FFT sizes, with the length changeable on every frame.

Availability and licensing#

fft_64k is available immediately under a project license. Contact us with your transform lengths, overlap and target device for pricing.

Full design document#

The full design document, covering detailed timing, configuration options and integration guidance, is available on request. Email info@dilloneng.com or see our contact page.