FPGA and ASIC DSP design#

Custom implementation of DSP algorithms in FPGAs and ASICs, with emphasis on high-bandwidth, real-time signal and image processing.

What we do#

  • Algorithm analysis and partitioning for hardware

  • Fixed- and floating-point architecture trade studies

  • RTL design, timing closure and resource optimization

  • Bit-accurate modeling and verification against your reference

  • Custom IP core development and integration support

How an engagement works#

  1. Scope: your algorithm, interfaces, target device and performance goals.

  2. Model: a bit-accurate model agreed with you before any RTL is written.

  3. Implement: parameterized RTL, verified against the model.

  4. Deliver: source or netlist, testbench, documentation and support.