Dillon Engineering
Home
Company
About Us
Contact Us
Jobs
Services
Applications
Markets
Why Hire DE?
>
Top Down Meets Bottom Up
When to Hire DE?
FFT IP
Load Unload FFT
UltraLong FFT
>
UltraLong FFT IP Core for Xilinx FPGAs
Parallel FFT
Dual Parallel FFT
Parallel Butterfly FFT
Mixed Radix FFT
>
Mixed Radix FFT IP Core for Xilinx FPGAs
Pipelined FFT
>
FFT_PIPE IP Core for Xilinx FPGAs
2D FFT
Other IP Cores
>
Floating Point IP
>
FPLIC Riviera Evaluation
FPLIC Download
FPLIC ParaCore Parameters
AES Crypto IP
>
AES PatraCore Parameters
AES Background Information
FFT/IFFT ParaCore Parameters
Ingenuity
ParaCore Architect IP Generation
>
PCA Flow
PCA Example
Modeling
Verification
Fixed vs. Floating Point
Fixed Point Math
News
DE Releases Mixed Radix FFT IP Cores for Xilinx FPGAs
DE Release UltraLong FFT IP Cores for Xilinx FPGAs
DE Releases FFT_PIPE IP Cores for Xilinx FPGAs
Floating Point Modules Evaluation Available
Chip Design Magazine Article
BCD Math
UltraLong FFT IP Success
DE Releases FFT IP Cores
Docs
HowTo
>
Power Calculation Using XPower
Strings in Verilog
Inferring Block RAM vs. Distributed RAM in XST and Precision
Verilog RTL Coding Style Guidelines, Tips and Template
Downloads
>
gen_ise-sh
gen-ise-sh-py
deModel
deModel_tar_gz
deModel_win32_exe
HPEC Presentations
>
HPEC 2003 Presentation
HPEC 2004 Presentation
HPEC 2007 Abstract
HPEC 2007 Posters
FFT
>
Load Unload FFT IP Datasheet
FFT_MIXED Candidate Core Datasheet
DE FFT IP and Sundance SMT702 Flyer
UltraLong FFT IP Core for Xilinx Datasheet
PIPE_FFT for Xilinx FPGAs Datasheet
FFT Datasheet
Floating Point FFT Factsheet
FFT Success
Sundance DE Partnership Release
FPGA Webcast
FPGAs Go, Go, Go
AES Datasheet
FPLIC Specification
DE Overview
deModel_win32_exe
deModel windows 32 installer
demodel-0.2.win32.exe
File Size:
70 kb
File Type:
exe
Download File
