Published: November 5, 2024

Floating Point Modules Evaluation Available

Product Announcement

Dillon Engineering has released for immediate download evaluation libraries for Aldec Riviera simulation of its Floating Point Library IP Core (FPLIC). Engineers can now evaluate the complete FPLIC library with pre-compiled encrypted models for comprehensive functional verification.

FPLIC Evaluation Package

The FPLIC Evaluation Library provides a complete environment for evaluating Dillon Engineering's floating-point arithmetic IP cores. This free evaluation package enables designers to thoroughly test FPLIC modules in their applications before committing to a license.

What's Included

Pre-Compiled Libraries: Encrypted VHDL and Verilog libraries for simulation
Complete Function Set: All FPLIC operations available for evaluation
Comprehensive Testbenches: Example testbenches demonstrating each function
Test Vectors: Extensive test vector suite with known results
Documentation: User guide and API reference
Example Designs: Sample integration examples
30-Day License: Full-featured evaluation period

Supported Operations

Basic Arithmetic

Operation	Single Precision	Double Precision
Addition	✓	✓
Subtraction	✓	✓
Multiplication	✓	✓
Division	✓	✓
Square Root	✓	✓

Advanced Functions

Reciprocal (1/x)
Reciprocal square root (1/√x)
Exponential (e^x)
Natural logarithm (ln x)
Power function (x^y)

Conversion Operations

Fixed-point to floating-point
Floating-point to fixed-point
Integer to floating-point
Floating-point to integer
Single to double precision
Double to single precision

Comparison Operations

Equal (==)
Not equal (!=)
Less than (<)
Less than or equal (<=)
Greater than (>)
Greater than or equal (>=)

Aldec Riviera-PRO Support

Why Riviera-PRO?

Aldec Riviera-PRO is a high-performance HDL simulator that provides:

Fast simulation performance for large designs
Support for mixed-language designs (VHDL/Verilog/SystemVerilog)
Advanced debugging capabilities
Code coverage analysis
Integration with popular FPGA tools

Installation and Setup

The evaluation package includes simple setup instructions:

Download the FPLIC evaluation package
Extract to your working directory
Source the setup script for Riviera-PRO
Compile the provided testbenches
Run simulations and analyze results

Getting Started

Quick Start Example

The evaluation package includes a quick start example demonstrating floating-point addition:

-- VHDL Example: Floating Point Addition
library ieee;
use ieee.std_logic_1164.all;
library fplic;
use fplic.fplic_pkg.all;

entity fp_add_example is
end fp_add_example;

architecture behavior of fp_add_example is
    signal clk : std_logic := '0';
    signal a, b, result : std_logic_vector(31 downto 0);
    signal valid_in, valid_out : std_logic;
begin
    -- Clock generation
    clk <= not clk after 5 ns;
    
    -- Instantiate FPLIC adder
    fp_adder: entity fplic.fp_add_sp
    port map (
        clk => clk,
        valid_in => valid_in,
        a => a,
        b => b,
        result => result,
        valid_out => valid_out
    );
    
    -- Test stimulus
    process
    begin
        valid_in <= '0';
        wait for 20 ns;
        
        -- Test case: 3.14 + 2.71
        a <= X"4048F5C3";  -- 3.14 in IEEE 754
        b <= X"402D70A4";  -- 2.71 in IEEE 754
        valid_in <= '1';
        wait for 10 ns;
        valid_in <= '0';
        
        wait for 100 ns;
        -- Result should be 5.85
        
        wait;
    end process;
end behavior;
            

Running Simulations

To run the example simulations:

# Compile the libraries
vlib fplic_lib
vmap fplic fplic_lib

# Compile FPLIC evaluation library
vcom -work fplic fplic_eval.vhd

# Compile and run testbench
vcom fp_add_example.vhd
vsim fp_add_example
run -all
            

Evaluation Features

Full Functional Verification

The evaluation library provides complete functionality:

All operations work exactly as production version
Same latency and timing characteristics
IEEE 754 compliance verified
Exception handling fully functional
All rounding modes supported

Comprehensive Testing

Included test suites cover:

Basic Functionality: Standard test cases for each operation
Edge Cases: Infinity, NaN, denormalized numbers
Random Testing: Thousands of random test vectors
Comparison Testing: Results compared against reference implementation
Performance Testing: Throughput and latency measurements

Transitioning to Production

After Evaluation

Once you've completed your evaluation, transitioning to production is straightforward:

Same Interface: Production libraries use identical interfaces
Same Performance: No changes in timing or resource usage
Additional Formats: Source code and synthesis-ready versions available
Broader Support: Production licenses include support for multiple simulators
Technical Support: Full technical support and integration assistance

Licensing Options

Multiple licensing options available:

Project License: Single product use
Multi-Project License: Multiple projects within organization
Site License: Unlimited use at one location
Source Code License: Includes modifiable RTL

Additional Simulator Support

While this announcement focuses on Riviera-PRO, FPLIC is also available for:

Xilinx Vivado Simulator
ModelSim/QuestaSim (Mentor Graphics)
Cadence Xcelium
Synopsys VCS

Contact Dillon Engineering for evaluation packages for other simulators.

Technical Support

Evaluation Support

Even during evaluation, Dillon Engineering provides support:

Email support for installation and setup questions
Documentation and user guides
Example designs and application notes
FAQ and troubleshooting resources

Migration Assistance

We help you transition from software to hardware floating-point:

Algorithm analysis and optimization
Precision requirement analysis
Performance estimation
Integration consulting

Success Stories

Customer Testimonial

"The FPLIC evaluation package made it easy to verify that floating-point arithmetic would work for our application. The pre-compiled libraries integrated seamlessly with our existing testbenches, and the comprehensive test vectors gave us confidence in the IP's correctness. We moved from evaluation to production license within two weeks."

— Senior FPGA Engineer, Medical Imaging Company

Download Today

Get Your Free Evaluation

Download the FPLIC evaluation package today and start exploring high-performance floating-point arithmetic for your FPGA designs. No registration required, no commitments - just download and start evaluating.

Package Contents:

Pre-compiled Riviera-PRO libraries
Complete testbench suite
User documentation
Example designs
30-day evaluation license

Download Evaluation Package

Questions? Email: info@dilloneng.com

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