Fast Fourier Transform (FFT) IP Cores for FPGA and ASIC
World's fastest FFT/IFFT IP Cores with both fixed and floating point capabilities.
Dillon Engineering has the most extensive supply of FFT/IFFT IP Cores for FPGA and ASIC to meet the needs of the most demanding applications. Review the information about our IP and feel free to contact us with any questions you may have.
Dillon Engineering’s Fast Fourier Transform (FFT) IP Cores have been developed using our state-of-the-art ParaCore Architect™ utility. The result is highly parameterized cores that can be quickly and easily tailored to meet the size, performance, and data processing needs of any application. By means of ParaCore Architect™, our FFT cores can also be quickly and easily re-targeted towards any FPGA or ASIC technology.
Dillon Engineering has the most extensive supply of FFT/IFFT IP Cores for FPGA and ASIC to meet the needs of the most demanding applications. Review the information about our IP and feel free to contact us with any questions you may have.
Dillon Engineering’s Fast Fourier Transform (FFT) IP Cores have been developed using our state-of-the-art ParaCore Architect™ utility. The result is highly parameterized cores that can be quickly and easily tailored to meet the size, performance, and data processing needs of any application. By means of ParaCore Architect™, our FFT cores can also be quickly and easily re-targeted towards any FPGA or ASIC technology.
FFT Architectures
Dillon Engineering has an FFT architecture available as an IP Core for any application. The table compares the architectures available, follow the link to obtain more detailed information about any architecture.
| Architecture |
Speed |
Memory Usage |
Logic Usage |
Comments |
|---|---|---|---|---|
| Full Parallel |
Fast |
None |
Low |
Constant twiddle factors reduce multiplier complexity and
logic usage, 25 GSPS+ potential in large Virtex-5 FPGA. Useful for
shorter lengths, practical up to 128 points. |
| Dual Parallel |
Fast |
Medium |
Low |
Two parallel FFT cores, in series with shuffle memory in
between. Requires input/output buffers for natural ordered I/O. Extends
parallel architecture lengths up to 2K or 4K points. |
| Parallel Butterfly |
Medium |
High |
Medium |
Bank of butterflies execute a
rank at a time. Multiple I/O streams increase performance beyond single
point per clock cycle. |
| UltraLong |
Medium |
High |
Medium |
External memory used with two FFT engines. Throughput normally
limited by external memory bandwidth. |
| 2D FFT |
Medium |
Medium |
Medium |
Two dimensional FFT, uses internal or external memory between two FFT
engines. Throughput normally limited by memory bandwidth. |
| Mixed Radix |
Medium |
Medium |
Medium |
Used for lengths other than radix-2 lengths. Combinations of
radix-2, 3, 5, and 7 are available. |
| Pipelined |
Medium |
Low |
Medium |
One butterfly per rank pipelined
architecture, useful for continuous-stream low memory usage
applications. |
Fixed or Floating Point FFT
Our FFT IP cores are available in any bit-width fixed point, as well as in single-, double-, or custom-precision floating point. With floating point math performed in hardware, logic utilization becomes the primary issue. Using fully pipelined floating point math operators, such as from our IEEE 754 Floating Point IP Library, we achieve the same throughput performance with floating point FFT as we do with fixed point FFT, provided the device supports the increased logic size for the equivalent math operators.
Device Fit Estimate of Additional Informaiton
Fill out the FFT IP Fit/Information Form to obtain a device usage estimate in your target technology or to obtain additional information about a specific FFT architecture.
Other IP Cores
In addition to the FFT IP found here, Dillon Engineering offers pre-designed IEEE 754 Floating Point Modules.
