Verilog RTL Coding Style Guidelines, Tips, and Template

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Many companies create Verilog coding standards, usually developing these in specification ("thou shall") format. Some standards or guidelines are available on the web. What is lacking with a specification is a generic template of actual Verilog that can be used to start creating consistent RTL. This document contains simple code and some of the most common RTL design components, with a few tips to help start making good, reusable Verilog RTL code. Disclaimer: this code does not do anything that makes any sense, and some of the signals aren't used or terminated, etc.

Click  here to get the file.