Modeling
Rapid development of a golden algorithm representation that is utilized and maintained throughout the project.
Dillon Engineering Flow Context
The typical Dillon Engineering DSP/HPEC/algorithm-to-logic project flow will involve the creation of a model in a higher-level language (HLL). The term "model" is not rigidly defined, thus can mean different things in different contexts. Models can be developed as disposable prototypes or as conceptual representations that lack details and are based on assumptions. In our context, the model is a "golden" behaviorally exact, bit-accurate representation of the logic hardware description language (HDL) code that will be implemented in FPGA or ASIC. The model is generally the first thing that is developed, but it is also maintained right alongside any other algorithm or HDL source code throughout the project.
Benefits of modelling
The benefits of starting from a model instead of HDL are numerous. In a model, it's all about the data and the math operations. There are no clock cycles to worry about, no low-level hardware elements, no complex data-movement state machines to coordinate. In an intuitive, readable, lightweight, highly productive environment such as Python (read further), all of these benefits are realized:
If your algorithm does not yet exist in HLL form, we can assist in developing your algorithm to a "virtual prototype" stage using Python (read further) or another HLL. But if you have already developed an algorithm, it means you likely already have existing HLL code, such as M-code or C/C++. One question you may have is why would it be beneficial to maintain another source format of the algorithm?
When perfecting an algorithm, ease-of-development is the primary productivity issue. Now, when taking the leap from HLL to HDL, the big schedule and risk hitter will shift to become the commonality between the HLL and HDL. The larger the separation between these languages or the more details hidden within the HLL, the harder it will be to hand-craft and verify an equivalent HDL design.
Thus, the modeling environment needs to be based on top of well understood low-level libraries that operate lock-step and bit-accurate with the logic. It must bridge the gap from matrix to flat, sequential to concurrent, floating to fixed point. Our entire design environment, from logic design to modeling to verification, embodies this commonality.
Regarding an algorithm port to Python, a conversion from M-code to array-enhanced Python code generally looks very similar and thus is not that difficult to port. Read an introduction to Python advantages below.
A quick word on C/C++
As you may have gathered by now, our preferred modeling language from scratch is Python. We generally use C/C++ for simulation performance improvement (as it is easy to embed C calls within Python), or when C models are provided by or required by our customers. We understand C is ubiquitous and we fully support a C modeling flow, using our full gamut of bit-accurate libraries for C/C++ as we have with Python.
DE modeling compared to ESL and SystemC design tools
With increasing chip densities and complexity, a recent push in the industry is to raise logic device programming to the next layer of abstraction, via electronic system-level (ESL) design tools or hardware-aware HLL extensions such as SystemC. Ideally, a single HLL description becomes a unified source for algorithm development, verification, and logic device programming.
However, our modeling is based on data accuracy, in terms of replicating the exact mathematical intent of the algorithm. Modeling in our context does not provide timing, cycle accuracy, or other hardware awareness to the model. It is simply a fast, intuitive way to perform equivalent operations, with data comparisons controllable and observable at low-level operation boundaries.
Addressing our HDL designs versus those performed with ESL, our designs are typically very high performance. As such, they require intimate hardware knowledge and necessitate HDL coding at register transfer level (RTL). For productivity improvement of our design flow, we have developed our own high-level tool, ParaCore Architect, for parameterizing and optimizing IP core building blocks. Regarding current ESL tools, we acknowledge the difficulty of attempting to shoehorn von Neumann machine code into concurrent, parallel hardware, and we look forward to using the tools when performance nears that of RTL for our demanding design applications.
Introduction to Python
Python is an open-source design language, encompassing a lightweight scripting style liked by hardware engineers, but with extensions that include powerful array and scientific processing via NumPy / SciPy. Its concise, explicit format is easy to code, read, and maintain, resulting in excellent software quality. Object-oriented programming aspects promote powerful class creation and code reuse. The language is portable to all major platforms.
From what we have found, an engineer of any discipline can do more in less time with Python than with any other language. That is a bold statement, one that we believe is supported by the Python users community. For more information, start with http://wiki.python.org/moin/BeginnersGuide/Overview.
- Development speed. Code the essence of an algorithm in minutes. Use a wealth of libraries for encapsulation.
- Readability. Capture the essence of an algorithm in a highly intuitive page or two, not dozens of multi-page modules.
- Maintainability. Object-oriented features make tweakability and maintenance easy.
- Limitless data formats. Easily move between data types at any stage of the algorithm.
- Simulation speed. Achieve 10-100x speedup in verification CPU time.
If your algorithm does not yet exist in HLL form, we can assist in developing your algorithm to a "virtual prototype" stage using Python (read further) or another HLL. But if you have already developed an algorithm, it means you likely already have existing HLL code, such as M-code or C/C++. One question you may have is why would it be beneficial to maintain another source format of the algorithm?
When perfecting an algorithm, ease-of-development is the primary productivity issue. Now, when taking the leap from HLL to HDL, the big schedule and risk hitter will shift to become the commonality between the HLL and HDL. The larger the separation between these languages or the more details hidden within the HLL, the harder it will be to hand-craft and verify an equivalent HDL design.
Thus, the modeling environment needs to be based on top of well understood low-level libraries that operate lock-step and bit-accurate with the logic. It must bridge the gap from matrix to flat, sequential to concurrent, floating to fixed point. Our entire design environment, from logic design to modeling to verification, embodies this commonality.
Regarding an algorithm port to Python, a conversion from M-code to array-enhanced Python code generally looks very similar and thus is not that difficult to port. Read an introduction to Python advantages below.
A quick word on C/C++
As you may have gathered by now, our preferred modeling language from scratch is Python. We generally use C/C++ for simulation performance improvement (as it is easy to embed C calls within Python), or when C models are provided by or required by our customers. We understand C is ubiquitous and we fully support a C modeling flow, using our full gamut of bit-accurate libraries for C/C++ as we have with Python.
DE modeling compared to ESL and SystemC design tools
With increasing chip densities and complexity, a recent push in the industry is to raise logic device programming to the next layer of abstraction, via electronic system-level (ESL) design tools or hardware-aware HLL extensions such as SystemC. Ideally, a single HLL description becomes a unified source for algorithm development, verification, and logic device programming.
However, our modeling is based on data accuracy, in terms of replicating the exact mathematical intent of the algorithm. Modeling in our context does not provide timing, cycle accuracy, or other hardware awareness to the model. It is simply a fast, intuitive way to perform equivalent operations, with data comparisons controllable and observable at low-level operation boundaries.
Addressing our HDL designs versus those performed with ESL, our designs are typically very high performance. As such, they require intimate hardware knowledge and necessitate HDL coding at register transfer level (RTL). For productivity improvement of our design flow, we have developed our own high-level tool, ParaCore Architect, for parameterizing and optimizing IP core building blocks. Regarding current ESL tools, we acknowledge the difficulty of attempting to shoehorn von Neumann machine code into concurrent, parallel hardware, and we look forward to using the tools when performance nears that of RTL for our demanding design applications.
Introduction to Python
Python is an open-source design language, encompassing a lightweight scripting style liked by hardware engineers, but with extensions that include powerful array and scientific processing via NumPy / SciPy. Its concise, explicit format is easy to code, read, and maintain, resulting in excellent software quality. Object-oriented programming aspects promote powerful class creation and code reuse. The language is portable to all major platforms.
From what we have found, an engineer of any discipline can do more in less time with Python than with any other language. That is a bold statement, one that we believe is supported by the Python users community. For more information, start with http://wiki.python.org/moin/BeginnersGuide/Overview.